Vdd Rd Vin1 Q1 NMO Vin2 Q2 NMO Nmos NAN ATE 2. Print your circuit schematic showing voltages for all four input combination. Observe the output voltage value for each input combination. Then run a C.OP Bias Point simulation (use the added 2N7000 model in LTspice) on your design with the four possible input combinations for Vin1 and Vin2 to verify your gate. Choose Rd (drain current limit resistor) such that the drain currents of the NMO devices will be about 30mA when the is in a low state. Make a truth table showing the four possible combinations of Vin1 and Vin2 and the outputs. The input logic 1 = 9 volt and ground as a logic 0. For the NMO NAN gate shown below gate, using the 2N7000 MOFET LTspice model such that Vto = 2.0. ![]() ![]() 1 ECE2274 Pre-Lab for MOFET logic LTspice NAN ate, NOR ate, and CMO Inverter 1.
0 Comments
Leave a Reply. |